With the increasing complexity of integrated circuits, the critical dimension and layout space correspondingly are increasingly shrunk. In order to meet the increasing efficiency and volume density demands of super large scale integrated circuits, the increase of process density and the miniaturization of device still are a continuing challenge for semiconductor process and designers.
Since the critical dimension of current process has approximately reached the physical extreme of optical instruments, so that the steps such as locating, developing, etching and chemical mechanical polishing would not readily achieve expected accuracy like that in the traditional process. Therefore, for the circuit design, if the process extreme is not taken in consideration, it is more possible to cause the short channel effect (SCE), resulting in the problems of threshold voltage shift of transistor, punch-through effect and increasing of leakage current and thereby the process yield is degraded.
In order to improve the short channel effect, a pocket or halo implant structure is widely adopted. In particular, an n-type dopant is implanted into a p-type metal-oxide-semiconductor (PMOS) device while a p-type dopant is implanted into an NMOS device, the halo implant region of such dopant generally is at the periphery of drain and source neighboring the gate. As a result, the punch-through effect can be suppressed and the threshold voltage of device can be increased to thereby decrease the leakage current.
However, when the semiconductor device is operated in sub-threshold region, the reverse short channel effect adverse for the device would occur. This is because the pocket or halo implant would weak the drain induced barrier lowing effect, the halo implant over-compensates the threshold voltage of device, so that the driving capability of device is weakened, the power consumption is increased and causing timing violation.
In order to solve the above-mentioned problems, a conventional solution of increasing channel lengths of all devices has been proposed to relieve the phenomenon of threshold voltage increase caused by the reverse short channel effect in complementary MOS devices. However, the increase of channel length for all devices would result in the increase of critical dimension, which violates the design purpose of decreasing the process density.
Another conventional solution is to fix the operation voltage of integrated circuit in sub-threshold region and use the reverse short channel effect to shrink the transistor size, so as to save the layout area, reduce the capacitive loads of drain and source and improve the circuit power performance. However, such conventional solution would seriously limit the design flexibility and application range of logic circuit.
Accordingly, there is a need to provide an improved integrated circuit module and a manufacturing method and an application thereof, which is applicable in any range of operation voltage and can reduce the process density and manufacturing cost on the prerequisite of taking account of operation speed and power consumption.